Memory dies are commonly stacked to increase the memory density on a limited area of a substrate, for example within a standard-sized package. The resulting stacked devices are known as Multi-Chip Packages (MCP).
Referring to FIG. 1, one typical semiconductor device 100 has bonding pads 102 located around the periphery of each die 104. These dies 104 can be stacked and bonded using a simple interposer 106 to create sufficient space for a bonding wire 108 to reach one die 104 located underneath another die 104, and electrically connect the die 104 to a substrate 110.
Referring to FIG. 2, other semiconductor devices 200, such as NAND Flash, may have bonding pads 202 located along a single edge of each die 204. This eliminates the need for interposers entirely, since the dies 204 can be staggered or laterally offset from one another to expose the bonding pads 202 and allow bonding wire 208 access to each die 204 for electrical connection to a substrate 210.
However, high speed DDR DRAM devices, such as DDR3, have bonding pads located on the center spine of the die. Neither of the above techniques can be conveniently employed with such a bonding pad configuration, because the bonding pads of a lower die in the stack would be obstructed by higher dies in the stack, thereby preventing bonding wires from connecting the bonding pads to the substrate. As a result, the memory density of DRAM devices is effectively limited to the capacity of a single chip.
One approach to deal with this drawback is to connect the DRAM dies using through-silicon vias (TSVs). However, this approach requires a complex process to form the TSVs, which increases the cost of manufacture, adds manufacturing steps, and may decrease production yields. In addition, TSVs occupy area on the die, which may require redesigning the die to reconfigure the memory components, and which either increases the size or reduces the memory capacity of the die accordingly. Therefore, this method is not suitable for use with conventional DRAM dies.
Therefore, there is a need for a method of stacking DRAM dies such that all of the stacked dies can be connected to a common substrate.
There is also a need for a method of stacking semiconductor dies and bonding the dies to a common substrate, without requiring a particular bonding pad arrangement.
There is also a need for a multi-chip package having stacked DRAM dies that is simple to manufacture.